1. Field of the Invention
The present invention relates to a semiconductor device including insulated gate field effect transistors (hereinafter called the xe2x80x9cIGFETxe2x80x9d) and a method of manufacturing the same, and particularly to a semiconductor device including a plurality of IGFETs made of different gate insulating films and a method of such a semiconductor device. More specifically, the invention relates to a semiconductor device including at least a non-volatile memory circuit and a logic circuit mounted on a single substrate.
2. Description of the Related Art
Research and development have been made for a semiconductor device in which a non-volatile memory circuit and a logic circuit are integrated on a single substrate in order to enable free updating of stored information and high integration of circuits.
Non-volatile memory elements (memory cells) of non-volatile memory circuit having a two-layer electrode structure, and a non-volatile memory elements are made of a metal oxide semiconductor field effect transistor (called xe2x80x9cMOSFETxe2x80x9d hereinafter) which includes a charge storing gate electrode (a floating gate electrode) and a control gate electrode. The floating gate electrode is arranges on a tunnel insulating film formed on a channel forming region (a semiconductor substrate or a well region). The control gate electrode is arranged on an intermediate gate insulating film formed on a charge storing gate electrode.
The tunnel insulating film has been usually made of a pure silicon oxide film (SiO2) formed by thermal oxidation. Recently, an oxynitride film, which is produced by doping nitride atoms into a silicon oxide film through thermal nitridation, is often used as the tunnel insulating film. In the latter case, non-dangling bonds of the silicon oxide film, which result in hole trap caused by FN (Fowler-Nordheim) stress, are filled with nitride atoms, so that a fluctuation of current can be reduced compared with a pure silicon oxide film (tunnel insulating film) when a constant current is introduced. In other words, a non-volatile memory element can use a tunnel insulating film made of oxynitride, thereby improving charge storing performance after writing or erasing information.
On the other hand, the logic circuit is constituted by complementary MOSFET which is effective in reducing power consumption. In the complementary MOSFET, an n-channel MOSFET and a p-channel MOSFET have gate electrodes arranged at channel forming regions via gate insulating films. The gate insulating films are of pure silicon oxide films produced by the thermal oxidation.
Recently, the complementary MOSFET has the gate insulating film which is thinned for the purpose of minimization, and tends to adopt a dual gate electrode structure in order to suppress short channel effects accompanying the minimization. In the dual gate electrode structure, the gate electrode of the n-channel MOSFET is designed to have n-type conductivity, and the gate electrode of the p-channel MOSFET is designed to have the p-type conductivity. For example, arsenic (As) is used in order to obtain the n-channel MOSFET while boron (B) is used to obtain the p-channel MOSFET. As is an n-type impurity forming a source region and a drain region of the n-channel MOSFET, and can be doped into the gate electrode while the source and drain regions are being formed, which enables the n-type gate electrode to be produced without increasing the number of manufacturing steps. Further, B is p-type impurities used for forming source and drain regions in the p-channel MOSFET, and is doped into the gate electrode during the formation of the source and drain regions. This also enables the p-type gate electrode to be produced without an increase in the manufacturing steps.
With the foregoing dual gate electrode structure, B has a high diffusion speed, and leaks and diffuses into the channel forming region through the gate insulating film, which causes fluctuation of a threshold voltage. Especially, thinning of the gate insulated film tends to promote leakage of B. In order to overcome this technical problem, use of a gate insulating film including a minute oxynitride layer is being reviewed in order to prevent diffusion of B at least onto a surface layer.
The following matters have not been considered in a semiconductor device including the foregoing non-volatile memory circuit and logic circuit.
(1) In the non-volatile memory circuit, it is preferable to uniformly dope high density nitride atoms into a tunnel insulating film of a non-volatile memory element in order to reduce non-dangling bonds and improve charge storing capability. The non-volatile memory element of the non-volatile memory circuit should have one charge storing gate electrode and one control gate electrode while a complementary MOSFET of the logic circuit should have one gate electrode. When three gate electrode are simply laid in three layers, the number of manufacturing steps will be increased, and yield of manufactured products may be reduced. In order to overcome this problem, the charge storing gate electrode of the non-volatile memory element is prepared beforehand, and the control gate electrode of the non-volatile memory element and the gate electrode of the complementary MOSFET are formed in the same manufacturing step. In other words, a total of two gate electrodes are formed.
In the last mentioned method, the tunnel insulating film having a high nitride atom density is removed from the regions where the non-volatile memory element and the complementary MOSFET have been prepared. However, silicon nitride layers are produced in an interface between the tunnel insulating film and the semiconductor substrate or the well region under the tunnel insulating film due to combination of nitride atoms of the tunnel insulating film, and silicon atoms of a semiconductor substrate or a well region. The foregoing silicon nitride layers cannot be reliably removed. As a result, it has been very difficult to produce the gate insulating film having excellent quality.
(2) The nitride atom density may be lowered in order to reliably remove the tunnel insulating film from the complementary MOSFET forming region, which adversely causes an increase in the number of non-dangling bonds in the tunnel insulating film for the non-volatile memory element, and reduction in the charge storing performance of the non-volatile memory element.
(3) In order to form gate electrode layer in two layers, the charge storing gate electrode of the non-volatile memory element and the gate electrode of the complementary MOSFET are manufactured in the same step, and the control gate electrode of the non-volatile memory element is produced thereafter in another step. However, impurities for adjusting threshold voltages are doped into the channel forming region prior to formation of the gate electrode of the complementary MOSFET, and then a high temperature annealing process is carried out in a step for forming an intermediate insulating gate film of the non-volatile memory element, so that the impurities may be extensively diffused more than necessary. Further, in the foregoing dual gate structure, B doped into the gate electrode of the p-channel MOSFET extensively diffuses and leaks. As a result, there has been a problem in that the threshold voltage of the complementary MOSFET, particularly p-channel MOSFET, is very difficult to control.
The present has been contemplated in order to overcome the foregoing problems of the related art. It is a first object of the invention to provide a semiconductor device which includes an insulated gate field effect transistor (IGFET) suitable as a non-volatile memory element having excellent charge storing capability, and an IGFET suitable as a logic element for stabilizing a threshold voltage.
A second object of the invention is to provide a method of manufacturing the foregoing semiconductor device.
A third object of the invention is to provide a method of manufacturing a semiconductor device including an IGFET in which a gate insulating film having a high nitride density can be reliably removed from a region for forming a gate insulating film of a low nitride atom density when the gate insulating films have different densities.
It is a fourth object of the invention to provide a method of manufacturing a semiconductor device in which a non-volatile memory element constituting a non-volatile memory circuit has an improved information storing capability (charge storing capability). This method also meets the third object.
It is a fifth object of the invention to provide a method of manufacturing a semiconductor device in which a p-channel type complementary IGFET can stabilize a threshold voltage. This method also meets the third or fourth object.
It is a sixth object of the invention to provide a method of manufacturing a semiconductor device in which a p-channel type complementary IGFET can improve driving force (drivability). This method also satisfies the fifth object.
A seventh object of the invention is to provide a semiconductor device in which a tunnel insulating film of a non-volatile memory element can have an increased nitride atom density in order to extensively improve information storing capability. This method also meets any of the third to fifth objects.
An eighth object of the invention is to provide a method of manufacturing a semiconductor device in which gate insulating films are formed by a reduced number of steps in order to reduce the total number of manufacturing steps. This method also meets the third object.
A final object of the invention is to provide a method of manufacturing a semiconductor device in which a high voltage breakdown IGFET can be formed by a reduced number of steps in order to reduce the total number of manufacturing steps. This method also meets the third object.
According to a first feature of the invention, there is provided a semiconductor device comprising: a first IGFET including a first gate insulating film containing nitride atoms; and a second IGFET including a second gate insulating film which has a low nitride atom density compared with a density of nitride atoms in the first insulating gate film, and is provided on the same substrate together with the first IGFET. It is preferable that the first and second gate insulating films are oxynitride films. The first IGFET preferably constitutes a non-volatile memory element for a non-volatile memory circuit, and the second IGFET constitutes a logic element for a logic circuit. The first gate insulating film is preferably a tunnel insulating film. The logic element preferably includes a p-channel type IGFET. It is practical that the nitride atom density of the first gate insulating film of the first IGFET is 5% or more, and the nitride atom density of the second gate insulating film of the second IGFET is less than 5%.
In the foregoing semiconductor device, the first gate insulating film has the high nitride atom density so that the first IGFET with a reduced number of non-dangling bonds in the first gate insulating film. When the first IGFET is used to constitute a non-volatile memory element using the first gate insulating film as a tunnel insulating film, it is possible to improve the information storing capability of the non-volatile memory element. Further, the low nitride atom density in the second gate insulating film is effective in making the second gate insulating film denser in IGFET. When the second IGFET having the second gate insulating film or a preferably a p-channel type IGFET having a dual gate structure is applied to a logic element, it is possible to prevent leakage of p-type impurities doped into the gate electrode, for example, B. This is effective in stabilizing a threshold voltage of the p-channel type IGFET.
In accordance with a second feature of the invention, there is provided a of manufacturing a semiconductor device comprising the steps of: (a) forming a buffer silicon oxide film on first and second regions of a semiconductor substrate; (b) selectively removing the buffer silicon oxide film from the first region, and forming a first silicon oxide film on the first region, the first silicon oxide film being thinner than the buffer silicon oxide film; (c) doping nitride atoms into the first silicon oxide film and the buffer silicon oxide film on the first region, and forming a first gate insulating film using the first silicon oxide film containing the nitride atoms; (d) selectively removing the buffer silicone oxide film from the second region and forming a second silicon oxide film on the second region; (e) doping nitride atoms, having a density lower than a density of the nitride atoms of the first gate insulating film, into the second silicon oxide film, and forming a second gate insulating film using the second silicon oxide film containing doped nitride atoms; (f) forming a first IGFET on the first region; and (g) forming a second IGFET on the second region.
In this method, when the first gate insulating film having the high nitride atom density is formed on the first region of the semiconductor substrate, the second region is covered by the thick buffer silicon oxide film, so that it is possible to reduce an amount of nitride atoms reaching an interface between the second region and the buffer silicon oxide film. This is effective in preventing formation of a silicon nitride film on the interface between the second region and the buffer silicon oxide film. Therefore, the excellent second gate insulating film can be forced on the second region since the buffer silicon oxide film can be reliably removed (i.e. there is no silicon nitride film on the second region) after the first gate insulating film with the high nitride atom density has been formed.
According to a third feature, the step (f) in the second feature includes the step (h) of forming a charge storing gate electrode on the first gate insulating film in order to produce a non-volatile memory element which uses the first gate insulating film as a tunnel insulating film. It is preferable that the non-volatile memory element is an electrically erasable non-volatile memory element (EEPROM). Further, the non-volatile memory element may be a non-volatile memory element having a single electrode layer structure in which a charge storing gate electrode is constituted by a gate electrode layer and a control gate electrode is formed on a semiconductor region, and a non-volatile memory element having a two-layer gate electrode structure in which a control gate electrode is placed on a charge storing gate electrode with an intermediate gate insulating film sandwiched therebetween.
This feature is advantageous in that since the first gate insulating film having the high nitride atom density is used as the tunnel insulating film, it is possible to reduce non-dangling bonds, which cause hole trap, in the tunnel insulating film. This is effective in obtaining the non-volatile memory element having an improved charge storing capability. Further, this method enables production of the non-volatile memory element which has improved information writing and erasing capabilities, and also assure the advantage of the second feature.
In accordance with a fourth feature of the invention, the step (g) of the second or third feature includes the step of forming a p-channel type IGFET having a gate electrode in which p-channel type impurities are doped onto the second gate insulating film. B (boron) is practically usable as the p-type impurities. The gate electrode may be a single Si film or a single SiGe film, or a complex film formed a single Si film or a single SiGe film and a single refractory metal film or a single silicide film are laid on a single Si film or a single SiGe film. The second gate insulating film is required to have a region where nitride atoms are doped et least in the surface of the gate electrode.
This method is advantageous in the following respects in addition to the advantage accomplished by the first or second feature. The presence of nitride atoms in the second gate insulating film makes the second gate insulating film dense. The p-type impurities doped into the gate electrode, e.g. boron, can be protected against leakage. This enables production of the second IGFET having a stable threshold voltage.
In accordance with a fifth feature, the step (c) in the second to fourth feature is executed by making an oxynitride film having a peak nitride density of 5% or more. Further, the step (e) is executed by making an oxynitride film having a peak nitride density of less than 5%.
This method is advantages in the following respects besides the advantages attained by the second to fourth features. Since the second gate insulating film of the second IGFET, more specifically, p-channel type IGFET, is designed to have the peak value of the nitride atom density of less than 5%, it is possible to make the second gate insulating film denser. This is effective in preventing the leakage of the p-type impurities from the gate insulating film. Therefore, it is possible to produce the p-channel type IGFET which can have a stable threshold voltage that is practically usable without any problem. Further, the driving force of the p-channel type IGFET can be protected against reduction so that it is usable without any problem. Therefore, the p-channel type IGFET can control reduction of driving power to less than 10%.
According to a sixth feature, with the method of the second to fifth feature, the first silicon oxide film is annealed in the NH3 atmosphere in the step (c), and the second silicon oxide film is annealed in the N2O atmosphere in the step (e).
The annealing process in the NH3 atmosphere can make nitride atoms extensively dense in the first gate insulating film, which is effective in obtaining the non-volatile memory element which has a reduced number of non-dangling bonds in the tunnel insulating film and can improve the charge storing capability. Further, the annealing process in the N2O atmosphere can promote lowering of density of nitride atoms in the second gate insulating electrode, which can promote removal of the buffer silicon oxide film, so that the second gate insulating film having a good quality can be obtained.
In accordance with a seventh feature of the invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: (a) forming a buffer silicon oxide film on first and second regions of a semiconductor substrate; (b) selectively removing the buffer silicon oxide film from the first region, and forming a first silicon oxide film on the first region, the first silicon oxide film being thinner than the buffer silicon oxide film; (c) doping nitride atoms into the first silicon oxide film and the buffer silicon oxide film on the first region, and forming a first gate insulating film using the first silicon oxide film containing the nitride atoms; (d) forming a charge storing gate electrode on the first gate insulating film; (e) forming an intermediate gate insulating film on the charge storing gate electrode; (f) selectively removing the buffer silicon oxide film from the second region of the semiconductor substrate; (g) forming a second silicon oxide film on the second region of the semiconductor substrate; (h) doping nitride atoms, having a density lower than a density of the nitride atoms of the first gate insulating film, into the second silicon oxide film, and forming a second gate insulating film using the second silicon oxide film containing the nitride atom; and (i) simultaneously forming not only a control gate electrode on the intermediate gate insulating film in order to obtain a first IGFET, but also forming a gate electrode on the second gate insulating film in order to obtain a second IGFET.
In the step (i), the first IGFET is preferably formed in the same step as the step of forming the non-volatile memory element in the method according to the third feature, and the second IGFET is preferably formed by the same step as the step of forming the complementary IGFET. The step of forming the intermediate gate insulating film is preferably the same as the step of forming the silicon nitride film, silicon oxide film, and silicon nitride film one over after another on the charge storing gate.
This method is effective in the following respects in addition to the advantages accomplished by the first feature. The first gate insulating film of the first IGFET (e.g. the non-volatile memory element) is formed prior to the second gate insulating film of the second IGFET (e.g. complementary IGFET), so that the control gate electrode of the first IGFET and the gate electrode of the second IGFET can be simultaneously formed in the same manufacturing step. This is effective in reducing the number of the step for making the gate electrode layer and a total number of manufacturing steps.
Further, the first gate insulating film and intermediate gate insulating, film of the first IGFET are formed prior to the formation of the second gate insulating film of the second IGFET, so that it is possible to reduce an extent of the annealing process for the second IGFET. In other words, the annealing process can be reduced after the impurities for adjusting the threshold voltage are doped into the region for the second IGFET (i.e. the annealing processes for forming the tunnel insulating film and the intermediate gate insulating film are not carried out after the doping of the foregoing impurities). Therefore, it is possible to suppress unnecessary drive-in diffusion of the impurities, and to obtain the second IGFET having the stable threshold voltage (i.e. the threshold voltage of the second IGFET can be easily controlled).
According to an eighth feature of the invention, there is provided a method of manufacturing a semiconductor device comprising the steps of (a) forming a buffer silicon oxide film on first, second and third regions of a semiconductor substrate, (b) selectively removing the buffer silicon oxide film from the first region, and forming a first silicon oxide film on the first region, the first silicon oxide film being thinner than the buffer silicon oxide film; (c) selectively removing the buffer silicon oxide film from the second region and forming a second silicon oxide film on the second region, the second silicon oxide film being thinner than the buffer silicon oxide film; (d) making the third buffer silicon oxide film grow on the third region using the first and second silicon oxide films, and forming a third silicon oxide film, thicker than the first and second silicon oxide films, on the third region in order to produce a third gate insulating film using the third silicon oxide film; (e) doping nitride atoms into at least the first and silicon oxide films, and forming a first gate insulating film using the first silicon oxide film containing the nitride atoms in order to produce a second gate insulating film using the second silicon oxide film; (f) forming a first IGFET using the first gate insulating film; (g) forming a second IGFET using the second gate insulating film; and (h) forming a third IGFET using the third gate insulating film, the third IGFET having a higher breakdown voltage than breakdown voltages of the first and second IGFETs.
In this method, the second silicon oxide film is formed on the second region of the semiconductor substrate prior to doping nitride atoms into the first silicon oxide film at the first region. Then, the second gate insulating film is formed using the second silicon oxide film, so that it is not necessary to remove the oxynitride film from the second region after the first gate insulating electrode is formed by doping nitride atoms. Further, the first gate insulating film is formed at the first region of the semiconductor substrate. The buffer silicon film for obtaining the second gate electrode at the second region can be used to form the third gate insulating film on the high voltage breakdown IGFET at the third region. This is effective in reducing the number of steps of forming the gate insulating film and the total number of total manufacturing steps.
In a ninth feature of the invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: (a) forming a first gate insulating film containing nitride atoms on first and second regions of a semiconductor substrate; (b) removing the first gate insulating film from the second region; (c) forming a second gate insulating film on the second region, the second gate insulating film either containing nitride atoms whose density is lower than a density of nitride atoms in the first gate insulating film or being free from the nitride atoms; (d) forming a first gate electrode on the first gate insulating film on the first region in order to obtain a first IGFET; and (e) forming a second gate electrode on the second gate insulating film on the second region in order to obtain a second IGFET.
The first gate insulating film is preferably designed to have the nitride atom density so that non-dangling bonds can be sufficiently reduced at the first region and that the first gate insulating film can be reliably removed from the second region. For instance, the nitride atom density of the first insulating gate may be preferably less than 5%.
This method is advantageous in the following respects in addition to the advantage accomplished by the method of the second feature. The first gate insulating film which has a reduced number of non-dangling bonds at the first region and is reliably removed from the second region is formed all over the first and second regions of the semiconductor substrate. Therefore, the buffer silicon oxide film required in the method according to the second feature is dispensable in this method, which can reduce the total number of manufacturing steps.
According to a tenth feature of the invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: (a) forming a first gate insulating film containing nitride atoms on first, second and third regions of a semiconductor substrate; (b) removing the first gate insulating films from the second and third regions; (c) forming a second gate insulating film on the second region, the second gate insulating film either containing nitride atoms whose density is lower than a density of nitride atoms in the first gate insulating film or being free from the nitride atoms; (d) forming a third gate insulating film on the third region, the third gate insulating film having a higher breakdown voltage than the second gate insulating film, and containing nitride atoms whose density is lower than a density of nitride atoms in the first gate insulating film, or being free from the nitride atoms; (e) forming a first gate electrode on the first gate insulating film on the first region in order to obtain a first IGFET; (f) forming a second gate electrode on the second gate insulating film on the second region in order to obtain a second IGFET; and (g) forming a third gate electrode on the third gate insulating film on the third region in order to obtain a third IGFET.
This method is as advantageous as the method according to the ninth feature.